IEEE 1838-2019

IEEE 1838-2019 PDF

IEEE Std 1838(TM)-2019 standardizes mandatory and optional on-chip hardware components for 3D test access. It is intended that in the future a standard is developed for a formal, computer-readable language in which implementation choices for the three-dimensional design-for-test (3D-DfT) hardware can be specified and described. An idea of a language/data structure has been described in [B5]. The aim of IEEE Std 1838 is to define at die-level standardized and scalable 3D-DfT features based on and working with digital scan-based test access, such that when compliant dies are stacked, a stack-level 3D-DfT test access architecture emerges with a minimum functionality and many optional extensions. IEEE Std 1838 provides a modular test access architecture, in which dies and interconnect layers between adjacent stacked dies can be tested individually. The focus of the standard is testing the intra-die circuitry as well as the inter-die interconnects in pre-bond, mid-bond, and post-bond cases in pre-packaging, post-packaging, and boardlevel situations. The standard provides test access via a mandatory one-bit ('serial') input/output test port and optional multi-bit ('parallel') test ports. The standard is die-centric, i.e., compliance to the standard pertains to a die (and not to a stack of dies). Standardized die-level design-for-test (DfT) features comprise a stack-level test access architecture. In this way, the standard enables interoperability between die makers and stack maker. The standard does not address stack-level challenges and solutions. The most prominent example of this is that the standard does not address compliance of the stack to IEEE Std 1149.1(TM) boundary scan for board-level interconnect testing (although the standard certainly does not prohibit application thereof). IEEE Std 1838 does not mandate specific defect or fault models, specific test generation methods, nor specific die-internal 2D-DfT features. However, the standard leverages existing 2D-DfT wherever applicable and appropriate, including test access ports (such as specified in IEEE Std 1149.1), on-chip DfT such as internal scan chains and wrappers of embedded cores (such as specified in IEEE Std 1500(TM)), and on-chip design-for-debug and embedded instruments (such described in IEEE Std 1687). Stacking of dies requires that the vertical interconnects [e.g., micro-bumps and through-silicon vias (TSVs)] are aligned with respect to footprint (i.e., matching x,y layout locations), mechanical properties (i.e., matching materials, diameter, height, etc.), and electrical properties (i.e., matching driver/receiver pairs). As a generic DfT-only standard, IEEE Std 1838 does not govern these items. Similar to IEEE Std 1149.1 and IEEE Std 1500, it only defines a DfT architecture: - Number, name, type, and function of test I/Os - On-chip DfT hardware and corresponding description - Clock-cycle accurate test operation protocol For 3D-SICs, three parties are involved: Die Maker(s), Stack Maker(s), and Stack User(s). All circuit features of the stack are included in the individual die designs. Design and integration of test access features needs to be done by the Die Maker(s), not only to serve their own (pre-stacking) test objectives, but also to serve test objectives of Stack Maker and Stack User. After stacking, test (control and data) signals need to be able to travel from the stack's external I/Os up and down through the stack. Hence, the test access features in the various dies of the stack need to function in a concerted and interoperable fashion. Different dies might have their own technologies, design set-up, and test and design-for-test approaches; the standard should not modify those. The standard defines test access features for a die that enable the transportation of test stimuli and responses both for testing THIS DIE and its inter-die connections, as well as for testing OTHER DIES in the stack and their inter-die connections. New IEEE Standard - Active. IEEE Std 1838 is a die-centric standard; it applies to a die that is intended to be part of a multi-die stack. This standard defines die-level features that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is through-silicon vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding